1. Field of the Invention
The present invention relates generally to methods for forming patterned planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications. More particularly, the present invention relates to non-polishing methods for forming patterned planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications.
2. Description of the Related Art
Integrated circuit microelectronics fabrications are formed from semiconductor substrates within and upon whose surfaces are formed integrated circuit devices. The integrated circuit devices are connected internally and externally to the semiconductor substrates upon which they are formed through use of patterned conductor layers which are separated by dielectric layers.
As integrated circuit microelectronics fabrication integration levels have increased and integrated circuit device and patterned conductor layer dimensions have decreased, it has become more prevalent in the art of integrated circuit microelectronics fabrication to employ trench isolation methods, such as but not limited to shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods, to form planarized trench isolation regions within isolation trenches within semiconductor substrates in order to separate active regions of the semiconductor substrates within and upon which are formed integrated circuit devices.
Such shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are desirable for forming planarized trench isolation regions within isolation trenches within semiconductor substrates employed within integrated circuit microelectronics fabrications since shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods typically provide planarized trench isolation regions which are nominally co-planar with the surfaces of adjoining active regions of a semiconductor substrate which they separate. Such nominally coplanar planarized trench isolation regions and adjoining active regions of a semiconductor substrate generally optimize an attenuated depth of focus typically achievable with an advanced photoexposure apparatus employed when forming advanced integrated circuit devices and patterned conductor layers within an advanced integrated circuit microelectronics fabrication.
While shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are thus desirable when forming planarized trench isolation regions within isolation trenches within semiconductor substrates employed within advanced integrated circuit microelectronics fabrications, shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are nonetheless not entirely without problems when forming planarized trench isolation regions within isolation trenches within semiconductor substrates employed within advanced integrated circuit microelectronics fabrications. In particular, it is often difficult to form when employing shallow trench isolation (STI) methods which in turn employ chemical mechanical polish (CMP) planarizing methods for forming planarized trench isolation regions within isolation trenches within semiconductor substrates employed within integrated circuit microelectronics fabrications planarized trench isolation regions which are uniformly and economically planarized. In that regard, chemical mechanical polish (CMP) planarizing methods often provide non-uniformly chemical mechanical polish (CMP) planarized trench isolation regions, such as chemical mechanical polish (CMP) planarized trench isolation regions whose surfaces are dished, when such chemical mechanical polish (CMP) planarized trench isolation regions are formed within particularly wide isolation trenches of greater than about 300 microns width. In addition, chemical mechanical polish (CMP) planarizing methods also generally add complexity and cost to integrated circuit microelectronics fabrication methods, since such chemical mechanical polish (CMP) planarizing methods require additional integrated circuit microelectronics fabrication processing equipment and attendant capital expenditures.
It is therefore desirable within the art of integrated circuit microelectronics fabrication to provide non-polishing methods and materials through which planarized trench isolation regions may be formed within isolation trenches within semiconductor substrates employed within integrated circuit microelectronics fabrications to provide integrated circuit microelectronics fabrications fabricated with attenuated process complexity, attenuated integrated circuit microelectronics fabrication cost and enhanced planarized trench isolation region uniformity. In a more general sense, it is also desirable within the art of microelectronics fabrication, but not necessarily the art of integrated circuit microelectronics fabrication, to provide methods and materials through which planarized aperture fill layers, which need not necessarily be planarized trench isolation regions, may be formed within apertures within topographic substrate layers employed within microelectronics fabrications to provide microelectronics fabrications fabricated with attenuated process complexity, attenuated microelectronics fabrication cost and enhanced planarized aperture fill layer uniformity.
It is towards the foregoing objects that the present invention is both specifically and more generally directed.
Various planarizing methods have been disclosed in the art of integrated circuit microelectronics fabrication for forming planarized aperture fill layers within apertures within topographic substrate layers employed within integrated circuit microelectronics fabrications.
For example, Nag et al., in "Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25 .mu.m Technologies," IEDM 96, IEEE, pp. 841-44, compares a series of physical and electrical properties for each of several dielectric materials which may be employed within chemical mechanical polish (CMP) planarized trench isolation regions formed within isolation trenches within semiconductor substrates employed within integrated circuit microelectronics fabrications.
In addition, Avanzino et al., in U.S. Pat. No. 4,954,459, discloses a polishing planarizing method for forming a planarized aperture fill dielectric layer within an aperture, such as but not limited to an isolation trench, within a topographic substrate layer, such as but not limited to a semiconductor substrate, employed within an integrated circuit microelectronics fabrication. The method employs a conformal dielectric oxide layer formed over the topographic substrate layer, where upper lying portions of the conformal dielectric oxide layer corresponding with upper lying features of an underlying topography of the topographic substrate layer are selectively etched prior to a polish planarizing of the etched conformal dielectric oxide layer so formed.
Further, Haskall et al., in U.S. Pat. No. 4,962,064, discloses an alternative polish planarizing method for forming a planarized aperture fill dielectric layer within an aperture, such as but not limited to an isolation trench, within a topographic substrate layer, such as but not limited to a semiconductor substrate, employed within an integrated circuit microelectronics fabrication. The method employs a conformal dielectric oxide layer formed upon the topographic substrate layer, where the conformal dielectric oxide layer has a conformal planarizing material layer formed thereupon. An upper portion of the conformal planarizing material layer and a lower portion of the conformal planarizing material layer are then successively removed employing two separate polish planarizing process steps having interposed therebetween an etch process step which employs the lower portion of the conformal planarizing material layer as an etch mask layer.
Still further, Bose et al., in U.S. Pat. No. 5,492,858, discloses a polish planarizing method for forming a planarized trench isolation region within an isolation trench of high aspect ratio within a semiconductor substrate employed within an integrated circuit microelectronics fabrication. The method employs forming a silicon nitride trench liner layer within the isolation trench prior forming within the isolation trench a conformal oxide dielectric layer which is subsequently steam annealed and polish planarized to form the planarized trench isolation region exhibiting enhanced properties.
Still yet further, Jain, in U.S. Pat. No. 5,494,854, discloses a polish planarizing method for simultaneously planarizing a series of patterned conductor layers of equivalent thickness, but differing aspect ratios, formed within an integrated circuit microelectronics fabrication. The method employs forming a first gap filling dielectric layer for planarizing apertures formed interposed between at least the patterns which comprise a high aspect ratio portion of the patterned conductor layers, where the first gap filling dielectric layer has formed thereupon a second dielectric layer which is polish planarized with enhanced throughput, planarity and uniformity.
Finally, Kwon et al., in U.S. Pat. No. 5,665,635, discloses an etchback planarizing method for forming a planarized trench isolation region within an isolation trench within a semiconductor substrate employed within an integrated circuit microelectronics fabrication. The method employs a surface treatment of an isolation trench liner layer and an isolation trench masking layer in a fashion such that a trench fill dielectric layer when subsequently formed upon the isolation trench liner layer and the isolation trench masking layer is formed more rapidly within the isolation trench than upon the isolation trench masking layer, thus allowing the etchback planarizing method to efficiently form a planarized trench isolation region within the isolation trench.
Desirable within the art of integrated circuit microelectronics fabrication are non-polishing methods and materials through which planarized trench isolation regions may be formed within isolation trenches within semiconductor substrates employed within integrated circuit microelectronics fabrications to provide integrated circuit microelectronics fabrications fabricated with attenuated process complexity, attenuated integrated circuit microelectronics fabrication cost and enhanced planarized trench isolation region uniformity. More generally desirable within the art of microelectronics fabrication, but not necessarily the art of integrated circuit microelectronics fabrication, are methods and materials through which planarized aperture fill layers, but not necessarily planarized trench isolation regions, may be formed within apertures within topographic substrate layers employed within microelectronics fabrications to provide microelectronics fabrications fabricated with attenuated process complexity, attenuated microelectronics fabrication cost and enhanced planarized aperture fill layer uniformity.
It is towards the foregoing objects that the present invention is both specifically and more generally directed.